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c6de27e945
note that in order to make it work, some lesser-used functionality (clustering and CMIM) had to be disabled. This could be revisited in the future.
77 lines
1.7 KiB
Python
77 lines
1.7 KiB
Python
from rdkit.ML import FeatureSelect as FS
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from rdkit import DataStructs as DS
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from rdkit import RDConfig
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import unittest
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class TestCase(unittest.TestCase):
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def setUp(self) :
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pass
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def test0FromList(self) :
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examples = []
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bv = DS.ExplicitBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.ExplicitBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.ExplicitBitVect(5)
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bv.SetBitsFromList([0,3,4])
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examples.append([0,bv,1])
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bv = DS.ExplicitBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.ExplicitBitVect(5)
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bv.SetBitsFromList([0,2])
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examples.append([0,bv,1])
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r = FS.selectCMIM(examples,2)
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self.failUnlessEqual(r,(2,4))
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r = FS.selectCMIM(examples,1)
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self.failUnlessEqual(r,(2,))
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r = FS.selectCMIM(examples,3)
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self.failUnlessEqual(r,(2,4,-1))
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def test1FromList(self) :
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examples = []
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bv = DS.SparseBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.SparseBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.SparseBitVect(5)
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bv.SetBitsFromList([0,3,4])
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examples.append([0,bv,1])
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bv = DS.SparseBitVect(5)
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bv.SetBitsFromList([0,2,4])
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examples.append([0,bv,0])
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bv = DS.SparseBitVect(5)
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bv.SetBitsFromList([0,2])
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examples.append([0,bv,1])
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r = FS.selectCMIM(examples,2)
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self.failUnlessEqual(r,(2,4))
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r = FS.selectCMIM(examples,1)
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self.failUnlessEqual(r,(2,))
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r = FS.selectCMIM(examples,3)
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self.failUnlessEqual(r,(2,4,-1))
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if __name__ == '__main__':
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unittest.main()
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